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Section 11 Multi-Function Timer Pulse Unit 2
Page 498 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
11.3.22 Timer Dead Time Data Register (TDDR)
TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3
and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and
TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the
TCNT_3 counter and the count operation starts.
The initial value of TDDR is H'FFFF.
Bit:
Initial value:
R/W:
151413121110987654321
0
1111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.
11.3.23 Timer Cycle Data Register (TCDR)
TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync
value (a value of two times TDDR + 3 or greater) as the TCDR register value. This register is
constantly compared with the TCNTS counter in complementary PWM mode, and when a match
occurs, the TCNTS counter switches direction (decrement to increment).
The initial value of TCDR is H'FFFF.
Bit:
Initial value:
R/W:
151413121110987654321
0
1111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.