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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1007 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit 5 — Sleep Mode (MCR5): Enables or disables Sleep mode transition. If this bit is set, while
this module is in halt mode, the transition to sleep mode is enabled. Setting MCR5 is allowed after
entering Halt mode. The two Error Counters (REC, TEC) will remain the same during Sleep
mode. This mode will be exited in two ways:
1. by writing a '0' to this bit position,
2. or, if MCR[7] is enabled, after detecting a dominant bit on the CAN bus.
If Auto wake up mode is disabled, this module will ignore all CAN bus activities until the sleep
mode is terminated. When leaving this mode this module will synchronise to the CAN bus (by
checking for 11 recessive bits) before joining CAN Bus activity. This means that, when the No.2
method is used, this module will miss the first message to receive. CAN transceivers stand-by
mode will also be unable to cope with the first message when exiting stand by mode, and the S/W
needs to be designed in this manner.
In sleep mode only the following registers can be accessed: MCR, GSR, IRR and IMR.
Important: This module is required to be in Halt mode before requesting to enter in Sleep mode.
That allows the CPU to clear all pending interrupts before entering sleep mode. Once all interrupts
are cleared this module must leave the Halt mode and enter Sleep mode simultaneously (by
writing MCR[5] = 1 and MCR[1] = 0 at the same time).
Bit 5: MCR5 Description
0 This module sleep mode released (Initial value)
1 Transition to this module sleep mode enabled
Bit 4 — Reserved. The written value should always be '0' and the returned value is '0'.
Bit 3 — Reserved. The written value should always be '0' and the returned value is '0'.
Bit 2 — Message Transmission Priority (MCR2): MCR2 selects the order of transmission for
pending transmit data. If this bit is set, pending transmit data are sent in order of the bit position in
the Transmission Pending Register (TXPR). The order of transmission starts from Mailbox-31 as
the highest priority, and then down to Mailbox-1 (if those mailboxes are configured for
transmission). Please note that this feature cannot be used for time trigger transmission of the
Mailboxes 24 to 30.
If MCR2 is cleared, all messages for transmission are queued with respect to their priority (by
running internal arbitration). The highest priority message has the Arbitration Field (STDID + IDE
bit + EXTID (if IDE = 1) + RTR bit) with the lowest digital value and is transmitted first. The
internal arbitration includes the RTR bit and the IDE bit (internal arbitration works in the same