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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 417 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
10.4.3 Channel Priority
When this module receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. Two modes (fixed mode 1 and fixed mode 2)
are selected.
In these mode, the priority levels among the channels are as follows:
Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH8 > CH9 >
CH10 > CH11> CH12> CH13 > CH14 > CH15
Fixed mode 2: CH0 > CH8 > CH1 > CH9 > CH2 > CH10 > CH3 > CH11> CH4 >
CH12 > CH5 > CH13 > CH6> CH14 > CH7 > CH15
These are selected by the PR1 and PR0 bits in the DMA operation register (DMAOR).
10.4.4 DMA Transfer Types
DMA transfer has two types; single address mode transfer and dual address mode transfer. They
depend on the number of bus cycles of access to the transfer source and destination. A data
transfer timing depends on the bus mode, which is the cycle steal mode or burst mode. This
module supports the transfers shown in table 10.8.
Table 10.8 Supported DMA Transfers
Transfer Destination
Transfer Source
External
Device with
DACK
External
Memory
Memory-
Mapped
External Device
On-Chip
Peripheral
Module
On-Chip
Memory
External device
with DACK
Not available Dual, single Dual, single Dual Dual
External memory Dual, single Dual Dual Dual Dual
Memory-mapped
external device
Dual, single Dual Dual Dual Dual
On-chip
peripheral
module
Dual Dual Dual Dual Dual
On-chip memory Dual Dual Dual Dual Dual
Notes: 1. Dual: Dual address mode
2. Single: Single address mode
3. 16-byte transfer is available only for on-chip peripheral modules that support longword
access.