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Section 2 CPU
R01UH0134EJ0400 Rev. 4.00 Page 67 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Instruction Formats
Source
Operand
Destination
Operand
Example
nd4 format
xxxxxxxx dddd
15 0
nnnn
R0 (Register direct) nnnndddd:
Register indirect
with displacement
MOV.B
R0,@(disp,Rn)
nmd format
nnnn
xxxx dddd
15 0
mmmm
mmmm: Register
direct
nnnndddd: Register
indirect with
displacement
MOV.L
Rm,@(disp,Rn)
mmmmdddd:
Register indirect
with displacement
nnnn: Register
direct
MOV.L
@(disp,Rm),Rn
nmd12 format
xxxx dddd dddddddd
15
0
xxxx mmmm xxxxnnnn
32
16
mmmm: Register
direct
nnnndddd: Register
indirect with
displacement
MOV.L
Rm,@(disp12,Rn)
mmmmdddd:
Register indirect
with displacement
nnnn: Register
direct
MOV.L
@(disp12,Rm),Rn
d format
dddd
xxxx
15 0
xxxx
dddd
dddddddd: GBR
indirect with
displacement
R0 (Register direct) MOV.L
@(disp,GBR),R0
R0 (Register direct) dddddddd: GBR
indirect with
displacement
MOV.L
R0,@(disp,GBR)
dddddddd: PC
relative with
displacement
R0 (Register direct) MOVA
@(disp,PC),R0
dddddddd: TBR
duplicate indirect
with displacement
JSR/N
@@(disp8,TBR)
dddddddd: PC
relative
BF label
d12 format
dddd
xxxx
15 0
dddd dddd
dddddddddddd: PC
relative
BRA label
(label = disp +
PC)
nd8 format
dddd
nnnn
xxxx
15 0
dddd
dddddddd: PC
relative with
displacement
nnnn: Register
direct
MOV.L
@(disp,PC),Rn