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Section 26 USB 2.0 Host/Function Module
Page 1366 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
26.3.7 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)
CFIFO, D0FIFO and D1FIFO are port registers that are used to read data from the FIFO buffer
memory and writing data to the FIFO buffer memory.
There are three FIFO ports: the CFIFO, D0FIFO and D1FIFO ports. Each FIFO port is configured
of a port register (CFIFO, D0FIFO, D1FIFO) that handles reading of data from the FIFO buffer
memory and writing of data to the FIFO buffer memory, a select register (CFIFOSEL,
D0FIFOSEL, D1FIFOSEL) that is used to select the pipe assigned to the FIFO port, and a control
register (CFIFOCTR, D0FIFOCTR, D1FIFOCTR).
Each FIFO port has the following features.
The DCP FIFO buffer should be accessed through the CFIFO port.
Accessing the FIFO buffer using DMA transfer should be performed through the D0FIFO or
D1FIFO port.
The D1FIFO and D0FIFO ports can be accessed also by the CPU.
When using functions specific to the FIFO port, the pipe number (selected pipe) specified by
the CURPIPE bits cannot be changed (when the DMA transfer function is used, etc.).
Registers configuring a FIFO port do not affect other FIFO ports.
The same pipe should not be assigned to two or more FIFO ports.
There are two FIFO buffer states: the access right is on the CPU side and it is on the SIE side.
When the FIFO buffer access right is on the SIE side, the FIFO buffer cannot be accessed from
the CPU.
These registers are initialized by a power-on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FIFOPORT[15:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
Initial value:
R/W:
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FIFOPORT[31:16]