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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1593 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.16 Graphics Block Control Registers (GRCMEN1 and GRCMEN2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
R/WRRRRRRRRRRRRRRR
0000000000000000
RRRRRRRRRRRRRRR/WR/W
WE-----
-
----------
----- -----
- - - DEN VEN
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 WE 0 R/W Enables register value transfer.
Writing 1 to this bit transfers the values of registers
GRCMEN to GROPEDPHV (except GRCINTCNT)
and GROPBASERGB in synchronization with
Vsync. After register transfer is competed, this bit
is cleared to 0.
30 to 2 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1 DEN 0 R/W Enables display of the current layer (graphics
image 1 for GRCMEN1 or graphics image 2 for
GRCMEN2).
0: Disabled
1: Enabled
0 VEN 0 R/W Enables display of the lower layer (video input for
GRCMEN1 or overlaid graphics image 1 and video
input for GRCMEN2).
0: Disabled
1: Enabled