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Section 27 Video Display Controller 3
Page 1550 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
27.4 Configuration
This module consists of seven functional blocks listed in table 27.3. Figure 27.1 shows the entire
block diagram of this module.
Table 27.3 Functional Blocks
Block Name Overview of Functions
Input timing control
block
Selects the timing of the sync signal input with respect to the clock rising
or falling edge and selects the sync signal polarity. It also selects the
timing of the BT.601 and BT.656 video input signals with respect to the
clock rising or falling edge.
Video receiving block (1) Captures the input video and applies the scaling, contrast, and
brightness processing.
(2) Converts the YC format into the RGB565 format and stores the data
through the IV1-BUS.
(3) Applies field skipping processing, and stores the resultant data in the
RGB565 format through the IV1-BUS.
Video supplying block Reads video data through the IV2-BUS.
Graphics block 1 Reads a graphics image (layer 1) from the memory through the IV3-BUS,
overlays it on the video sent from the video supplying block, and outputs
the result to graphics block 2.
Graphics block 2 Reads a graphics image (layer 2) from the memory through the IV4-BUS,
overlays it on the output from graphics block 1, and outputs the result to
the panel control block.
Panel control block Generates the sync signals for output to the panel.
Output timing control
block
Controls the timing of the sync signal output with respect to the clock
rising or falling edge and controls the sync signal polarity. It also controls
the timing of the RGB666 video output signals with respect to the clock
rising or falling edge.