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Section 33 Power-Down Modes
R01UH0134EJ0400 Rev. 4.00 Page 1799 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
33.2.17 Deep Standby Cancel Source Select Register (DSSSR)
DSSSR is a 16-bit readable/writable register that consists of the bits for selecting a source to
cancel deep standby mode. The realtime clock alarm interrupt or change on the pins for canceling
(PC8 to PC5, PG11, PG10, PJ3, and PJ1) can be selected as a cancel source. The pins for
canceling can be used for canceling deep standby, regardless of pin function settings in the general
I/O port.
Note: When writing to this register, see section 33.4, Usage Notes.
1514131211109876543210
Bit:
Initial value:
R/W:
0000000000000000
R R R R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W
- - - - - PG11 PG10 - - RTCAR PC8 PC7 PC6 PC5 PJ1PJ3
Bit Bit Name
Initial
Value R/W Description
15 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10 PG11 0 R/W Cancel by Change on PG11
0: Deep standby mode is not canceled by change on
the PG11 pin.
1: Deep standby mode is canceled by change on the
PG11 pin.
Note: For 1-Mbyte version, this bit is reserved and
always read as 0. The write value should
always be 0.
9 PG10 0 R/W Cancel by Change on PG10
0: Deep standby mode is not canceled by change on
the PG10 pin.
1: Deep standby mode is canceled by change on the
PG10 pin.
Note: For 1-Mbyte version, this bit is reserved and
always read as 0. The write value should
always be 0.
8, 7 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.