Filter
Top Products
Section 9 Bus State Controller
Page 270 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
CS3WCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
RRRRRRRRRRRRRRRR
0000010100000000
R R/W R/W R R/W R/W R R/W R/W R R R/W R/W R R/W R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are
used in both areas in common.
*
----------------
- WTRP[1:0]* WTRCD[1:0]* TRWL[1:0]* WTRC[1:0]*- - A3CL[1:0] - - -
Bit Bit Name
Initial
Value R/W Description
31 to 15 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
14, 13 WTRP[1:0]* 00 R/W Number of Auto-Precharge Completion Wait Cycles
Specify the number of minimum precharge completion
wait cycles as shown below.
From the start of auto-precharge and issuing of
ACTV command for the same bank
From issuing of the PRE/PALL command to
issuing of the ACTV command for the same bank
Till entering the power-down mode or deep power-
down mode
From the issuing of PALL command to issuing
REF command in auto refresh mode
From the issuing of PALL command to issuing
SELF command in self refresh mode
The setting for areas 2 and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles