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ARCHITECTURE
AND
INSTRUCTIONS
Iteration Control
The iteration control transfer operations per-
form leading- and trailing-decision loop con-
trol.
The
destination
of
iteration
control
transfers must be within
-128
to +
127
bytes
from the instruction. These operations are par-
ticularly useful with string manipulation oper-
ations.
There are
four
iteration control transfer
operations provided:
LOOP
decrements the
CX
("count") register
by
one
and
transfers
if
CX
is
not zero.
LOOPZ
(also called
LOOPE)
decrements the
CX
register
by
one
and
transfers
if
CX
is
not
zero
and
the
ZF
flag
is
set (loop while zero
or
loop while equal).
LOOPNZ
(also called
LOOPNE)
decre-
ments the
CX
register by one
and
transfers if
CX
is
not
zero
and
the
ZF
flag
is
cleared
(loop while
not
zero
or
loop while not equal).
JCXZ
transfers if the
CX
register
is
zero.
Interrupts
Program
execution control may be trans-
ferred by means
of
operations similar in
effect
to
that
of
external interrupts. All inter-
rupts transfer by pushing the flag registers
onto
the stack (as in
PUSHF),
and
perform
an
indirect call
(of
the inter-segment variety)
through
an
interrupt vector table located
at
absolute locations 0 through
3FFH.
This vec-
tor
contains a four-byte element for each
of
up
to 256 different interrupt types.
There are three interrupt transfer operations
provided:
INT pushes the flag registers (as in
PUSHF),
clears the
TF
and
IF
flags,
and
transfers con-
trol
with
an
indirect call
through
anyone
of
the
256 vector elements. A one-byte form
of
this
instruction
is available
for
interrupt
type
3.
overflow).
If
the
OF
flag
is
cleared no opera-
tion takes place.
IRET transfers control
to
the
return
address
saved by a previous interrupt operation
and
restores the saved flag register (as in
POPF).
See
Chapter
3 for further details
on
interrupt
operations.
PROCESSOR CONTROL INSTRUCTIONS
Various instructions
and
mechanisms control
the processor
and
its interaction with its
environment.
Flag Operations
Seven operations provided
on
individual flag registers:
CLC
clears the
CF
flag.
operate directly
CMC
complements the
CF
flag.
STC
sets the
CF
flag.
CLD
clears the
DF
flag, causing the string
operations
to
auto-increment the operand
pointer.
CLI
clears the
IF
flag, disabling external
interrupts (except for the non-maskable
external interrupt.
STI
sets
the
IF
flag,
enabling
external
interrupts after the execution
of
the next
instruction.
Processor Halt
The
HLT
instruction
causes
the
8088
processor halt. The halt state is cleared by
RESET,
or
an enabled external interrupt,
or
NMI.
Processor Wait
The WAIT instruction causes the processor
to
enter a wait state if the signal
on
its
TEST
pin
is
not
asserted. The wait state may be
interrupted by
an
enabled external interrupt.
When
this occurs the saved code location
is
that
of
the
WAIT
instruction, so
that
upon
INTO
pushes
the
flag
registers
(as
in
return from the interrupting task the wait
PUSHF),
clears the
TF
and
IF
flags,
and
state
is
reentered. The wait state
is
asserted.
transfers control with
an
indirect call
through
Execution resumes without allowing external
vector element 4
if
the
OF
flag
is
set (trap
on
interrupts until after the execution
of
the next
2-16