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HARDWARE DESIGN
CLK
(see note
3)
(see note
4)
~--~~r------~s
PULSE
1
PULS.E..2
MASTER
RO
CPU
GT
PULSE
3
MASTER
ITT
Master request is sampled
by
8088
(see note
1)
Master grant is sampled
by
8088
1.
THE
8088
FLOATS
S2,
51,
So
FROM
1.1.1
STATE
ON
THIS
EDGE
2.
THE
8088
FLOATS AxDx
BUS,RD,AND
LOCK
ON
THIS
EDGE
3.
THE
OTHER
MASTER
FLOATS
S2,
51,
SO
FROM
1.1.1
STATE
ON
THIS
EDGE
4.
THE
OTHER
MASTER
FLOATS AxDx
BUS,
AND
LOCK
ON
THIS
EDGE
Figure 3-33. Request/Grant Sequence Timing (Maximum Mode Only)
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