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HARDWARE DESIGN
This signal floats to 3-state
OFF
during "hold
acknowledge"
(Fig.
3-5).
INTR. Interrupt Request
is
a level-triggered
active
HIGH
input, sampled during the last
clock cycle of each instruction.
It
tells the
8088
to stop what
it
is
currently doing and
service
an
110 or peripheral device.
880.
This
is
a status output. When decoded
with IO
I M and D
RI
R,
SSO
specifies the
type of bus activity in progress (Fig.3-6).
IO/iiii
OT/R
550
1(HIGH)
0
0
Interrupt Acknowledge
When
INTR
is
detected HIGH, the
8088
jumps to an interrupt service routine via an
interrupt vector table in system memory.
INTR
can be internally masked through
software by resetting the interrupt enable bit
in the Flag register.
INTR
is
internally
synchronized.
1
1
1
O(lOW)
0
0
0
0
1
1
0
0
1
1
1 Read 1/0 port
0
Write 1/0 port
1
Halt
0 Code access
1 Read memory
0
Write memory
1 Passive
INT A. Used as a read strobe during interrupt
acknowledge cycles, INT A
is
active· LOW
during T2, T3, and T4 of each interrupt
acknowledge cycle. INT A
is
never floated.
Figure 3-6. iAPX
88
Status Decoding
ALE
STB
A19-
8282
I
A16-A19
A16
STB
A15-
8282
I
A8-A15
Vec
r
D
1
8088
A8
CPU
STB
AD7-
8282
I
AO-A7
I
8284A
ADO
CLOCK
I-+-
ClK
I
I
-n
GENERATOR
I-+-
READY
I
~
RES
I-+-
RESET
8286·1
00-07
ROY
T
OEI
A
A
A
I
+
INTA
DT/A"
• r
GND
INTR
DEN
~
HOLD
101M
-
-
HLDA
RD
-
-
WR
I
I I
,..
NMI
TEST
-
"
,
,
WRRDCS
J.IWRRDCE
WR
RDCS
I<=-
INTR
PERIPHERAL
DATA
HLDA
If
MEMORY
1<==
HOLD
INTR
INTA
ADDRESS
t
Figure 3-5. iAPX
88
with Buffered Demultiplexed Busses
3-5
)