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Table 1. Pin Description (Continued)
The
following pin function descriptions are for the
8088,
8228 system in maximum mode (i.e., MNIMX=GND.) Only the
pin
functions which are unique to maximum mode are described; all other pin functions are as described above.
Symbol
Pin No. Type
82,81,80
26-2B
RQ/GTO,
RQ/GT1
30,31
o
I/O
Name and Function
Status: is active during clock high of
T4, T1,
and
T2,
and is returned
to
the passive state.
(1,1,1) during T3
or
during
Tw
when READY is
HIGH.
This status is used by the
B2BB
bus con-
troller
to
generate all memory and
I/O
access
control signals. Any change by 82,
81,
or
SO
during
T4
is used
to
indicate the beginning
of
a
bus cycle, and the return
to
the passive state
in
T3
or
Tw
is used to indicate the end
of
a bus
cycle.
These signals float to 3-state OFF during
"hold
acknowledge". During the first
clock
cycle after
RESET becomes active, these signals are active
HIGH. After this first clock, they float to 3·state
OFF.
S2
S1
o
(LOW)
,
, ,
,
1
,
1
~
(HIGH)
,
,
,
1
1 1
"
CHARACTERISTICS
,
Interrupt Acknowledge
1
Read
110
pori
,
::~e~oport
1
,
CodeacceS$
1
Aead"!amory
,
Write memory
,
Pa'$ive
Request/Grant: pins are used by other local bus masters to force the processor
to
release the local bus at the end
of
the processor's current bus cycle. Each pin
is bidirectional with
RQ/GTO
having higher priority than RQ/GT1. RQ/GT has
an
internal pull-up resistor, so may
be
left unconnected. The request/grant se-
quence is as
follows (See Figure
B):
1.
A pulse
of
one CLK wide from another local bus master indicates a local bus
request
("hold")
to the
BOBB
(pulse
1).
2.
During a T4
or
TI
clock cycle, a pulse one
clock
wide from the
BOBB
to
the
requesting master (pulse
2),
indicates that the
BOBB
has allowed the local bus
to float and that
it
will enter the
"hold
acknowledge" state at the next CLK.
The CPU's bus interface
unit
is disconnected logically from the local bus
during
"hold
acknowledge". The same rules
as
for HOLD/HOLDAapply as
for
when the bus is released.
3.
A pulse one CLK wide from the requesting master indicates to the
BOBB
(pulse
3)
that the
"hold"
request is about to end and that the
BOBB
can reclaim-the
local
bus at the next CLK. The
CPU
then enters
T4.
Each master-master exchange
of
the local bus is a sequence
of
three pulses.
There must be one
idle CLK cycle after each bus exchange. Pulses are active
LOW.
If the request is made while the
CPU
is performing a memory cycle, it will release
the
local bus during T4
of
the cycle when all the following conditions are met:
1.
Request occurs on
or
before T2.
2.
Current cycle is not the
low
bit
of
a word.
3.
Current cycle is not the first acknowledge
of
an
interrupt acknowledge
sequence.
4.
A locked instruction is
not
currently executing.
If the local bus is idle when the request is made the two possible events will
follow:
1.
Local bus will
be
released during the next clock.
2.
A memory cycle will start within 3 clocks. Now the
four
rules
for
a currently
active memory cycle apply with condition number 1 already satisfied.
40
AFN·00826D