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HARDWARE DESIGN
drive specified to drive 2.0mA and 100pF, a
system with 5 peripheral components and
10
memory components would overload the
bus.
The 8282 non-inverting and
8283
inverting
octal latches plus the 8286 non-inverting and
8287 inverting octal transceivers can drive
loads up to 32mA and
300pF. The 8282/8283
are directly controlled by connecting ALE to
the STB (strobe) input and grounding
OE.
The 8286/8287
is
controlled by connecting
the
8088's
DEN
and
DT/R
signals to the
8286/8287's EN (enable) and T (transmit
inputs). These signals provide the proper tim-
ing to guarantee that the address
is
latched
properly and that the 8286/8287 drives data
in the correct direction for read and write
cycles.
Note that adding these latches and transceiv-
ers increases the chip count and adds
propagation delays (25ns for the
8283
and
8287 and 35ns for the 8282 and 8286) that
subtract from the read
or
write access time
of
the system's memory and peripheral devices.
For
complete specifications of the 8283/8282
and 8286/8287
see
the data sheets in the
Appendix.
Memory Operands
The iAPX
88
directly operates
on
8-
or
16-bit
memory based variables. This means that a
MOVE
3,AX
2ND
CYCLE
1ST
CYCLE
15
87
0
I
65
I
43
I
16-BIT
REG
ISTER
FORMAT
65
43
c------
MEMORY
MAP
Figure
3-12.
How 16-bit Data is Arranged
within 8-bit memory
6
5
4
3
2
o
3-13
variable may occupy one or two bytes
of
memory (each byte
is
8-bits). Consequently,
8-bit operands are read
or
written in one
machine cycle, while 16-bit operands require
two bus cycles.
16-bit operands are stored in memory, with the
least significant byte (LSB) first and the most
significant byte (MSB) in the next location.
Figure 3-12 shows
that
when
the
16-bit
operand
6543
was moved from the AX register
to memory location
3,
the LSB
(43)
was moved
into location 3 by the first machine cycle, and
the
MSB
(65)
was moved to location 4 in the
next machine cycle.
Clock Generation
The
8088
requires a clock signal with fast rise
and fall times
(lOns maximum) between low
and high voltages.
The maximum clock frequency
of
the
8088
is
5 MHz, and 8 MHz for the 8088-2. The
recommended method for generating this
signal
is
to use Intel's 8284A clock generator.
USING 8284A
Either
an
external frequency source
or
a ser-
ies resonant crystal may be selected to drive
the 8284A. The selected source must oscillate
at 3X the desired
CPU
frequency.
To select the crystal inputs of the 8284A as
the frequency source for clock generation, the
F / C input to the 8284A must be strapped to
ground. The crystal should be connected
using the configuration shown in Figure
3-13.
8088
l1:-
CPU
510Q
-
8284A
t---
X1
0
ClK
ClK
X2
510Q
-=-
/
Figure
3-13.
Generating Clock Signal with 8284A