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HARDWARE
DESIGN
If
tighter tolerance between the mmimum
and maximum reset times
is
necessary, the
reset circuit shown in Figure
3-18
might be
used rather than the simple RC circuit. This
circuit provides a constant current source and
a linear charge rate on the capacitor, rather
than the inverse exponential charge rate of
the
RC
circuit. The maximum reset period
for this implementation
is
124
MS.
The 8284A synchronizes the reset input with
the
CPU
clock to generate the RESET signal
to the
CPU. This output
is
also available
as
a
general reset to the entire system. Reset has
no effect on any clock circuits in the 8284A.
+
~
I
8284A
RESET
RES
ClK
r
Fie
SYSTEM RESET
8088
RESET
ClK
READY
IMPLEMENTATION
AND
TIMING
As
discussed previously, the ready signal
is
used in the
iAPX
88
system to generate wait
states to accommodate slow memory and
I/O
devices. Ready
is
also used in mUltipro-
cessor systems to force the
CPU
to wait for
access
to
the system bus.
Figure 3-17. 8284A Reset
Circuit
The 8284A can be set up for systems using
synchronous or asynchronous ready signals
by strapping the ASYNCH input HIGH
(synchronous) or
LOW (asynchronous). To
use
the synchronous configuration, the de-
signer must analyze the ready timing to
insure that the setup and hold requirements
Vee
RESET
V
dV Ie
dT = C
T
R1
- DETERMINES CURRENT TO CHARGE C
R2
- VALUE NOT CRITICAL = 10K
Ic
= CHARGE CURRENT =
VbdD1~
D2-
T
1)
"'Vee-.
6
IF
All
SEMICONDUCTORS ARE SILICON, Ie '"
.~V
Figure 3-18. Constant Current on Reset
Circuit
3-16