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HARDWARE DESIGN
Aa-
A
15
These pins drive the next 8 address bits on
the address bus. They are not multiplexed
with other signals
and
are valid during the
entire machine cycle.
These lines float to 3-state
OFF
during inter-
rupt acknowledge and local bus "hold acknow-
ledge".
A
16
-A
19
A
16
through A
19
have two sets of functions.
First, at the beginning
of
each machine cycle,
these pins drive the upper 4 bits of the
iAPX
88's 20-bit address bus. These 4 address bits,
(not provided by other 8-bit microproces-
sors), together with the other 16-bits
of
address, enable the
iAPX
88
to directly
address 1 megabyte
of
memory. This
is
16
times more
than
8080,8085, Z80; MC6800"
and
MC6809".
The second function
of
these four pins
is
to
provide status information. After the address
has been latched, pins AI6
and
AJ7
change
their function to status signals
S3
and
S4.
These two signals can be decoded to deter-
mine which memory segment
is
being acces-
sed by the 8088 during the current machine
cycle (Fig. 3-3). This information could
be
used to enable memory, such that each of the
8088
CPU
ALE
A15r-----------~,
A8·A
15
4 segments could have its own megabyte
of
memory, extending the
iAPX
88
memory
space to 4 megabytes.
Status line S5 gives the state
of
the interrupt
flag. S6
is
always low. These status signals are
not necessary for normal operation
of
most
systems,
but
they
can
be
useful
for
diagnostics.
These lines float to 3-state
OFF
during local
bus "hold acknowledge." During interrupt ac-
knowledge, the address information is indeter-
minate, but the status information
is
valid.
POWER
The 8088 should have pin
40
connected to
+5V,
and
pins 1 and
20
are ground. Decou-
S3
S4
0 0
Alternate
(relative
to
the
ES
segment)
1
0
Stack (relative to the
SS
segment)
0
1
Code/None
(relative
to
the
CS
segment
or a default of zero)
1
1 Data (relative to the
OS
segment)
S5
=
IF
(interrupt
enable flag)
S6
= 0 (indicates the
8088
is on the bus)
Figure 3-3. Decoding
01
Status Signals
S3-S6
8088
CPU
ALE
A
151-----~_=__------"
A8·A15
ADO·AD7
DRIVE
ADDRESS
EARLY
AND
DATA
LATE
IN
EACH
BUS
CYCLE.
Figure 3-2.
Time
Multiplexing
of
Address
and
Data
*Z80
is
a registered trademark
of
Zilog Corporation.
**MC6800
and MC6809 are registered trademarks
of
Motorola Corporation.
3-2