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HARDWARE
DESIGN
Secondly, a multiplexed system
is
necessarily
small-
usually less than
15
components-
due to the limited drive capability of the
MOS parts which directly drive the bus.
Larger iAPX
88
systems will normally use a
demultiplexed and buffered bus configura-
tion, (Fig.
3-5).
In this configuration, the
8282
is
used to latch the address and hold it
on the address bus throughout the entire
machine
cycle.
The
8286
octal transceiver
buffers the data bus to provide the higher
drive capability necessary for large systems.
Small systems could eliminate this trans-
ceiver and the latch on address lines
As-A15.
Memory and Peripheral Interface
The
8088
uses
address, data and control
information to control and communicate
with system memory and peripheral compo-
nents. Some components connect directly to
the multiplexed Address/Data Bus, while
others have separate address and data pins
and must connect to a
demultiplexed bus.
Some interfacing methods for both multi-
plexed and demultiplexed busses follow.
MULTIPLEXED BUS SYSTEMS
The connection of two multiplexed bus com-
ponents (the 8755A and
8185)
is
given in
Figure
3-9.
These components receive both
address and data on the same pins. The
address
is
internally latched by the ALE con-
trol signal.
The data then flows in (write), or out (read) if
the device has been enabled using the CS
(chip select) and CE (chip enable) inputs.
Note that the RD, WR,
IO/M
and ALE con-
trol signals from the
8088
CPU connect
directly to these chips.
Linear Chip Select
Connecting
A19
to CE2 of the 8755A in Fig.
3-9
enables this device whenever
A19
is
HIGH. CEI
is
grounded so
it
is
always valid.
3-9
The
8185
is
enabled whenever
All
is
LOW
and
A12
is
HIGH by connecting CS to
All,
CE2 to Al2, and CEI to ground.
Recall that address lines
As-A15
are held sta-
ble throughout the machine cycle and thus
can be connected directly
to
the chip enable
or chip select lines.
Linear chip select
is
a method that reduces
system chip complexity and chip count. At
the same time, linear chip selection reduces
available address space in the system.
For
instance a 2K memory
device,
the 8755A,
is
enabled by any address between
8000016
and
FFFFF16 (a 512K byte logical address space)
(Fig.
3-9).
This
is
usually not a problem
because most systems using the multiplexed
bus configuration are small enough that the I
megabyte address space of the iAPX
88
is
far
larger than necessary.
DE-MULTIPLEXED BUS SYSTEMS
Most system memories and peripherals re-
quire the address to be stable for the entire
machine cycle, therefore requiring address to
be latched and held on a separate de-
multiplexed address bus. Figure
3-10
shows
this system, with address lines AO-A7latched
by
an
8282
octal latch, which drives the lower
8 bits of the de-multiplexed address bus.
Note that the data bus
is
still multiplexed.
This brings up two things to consider.
First, multiplexed bus parts can still be used
in this system, provided they are connected to
the data bus.
Second, any devices connected to the data bus
must guarantee not to drive data onto this
bus before the ALE signal has latched the ad-
dress into the
8282
and the
8088
has 3-stated
its lower 8 address drivers
in
preparation for
reading the data.
If
a device were to drive the
data bus as soon as its address
is
generated,
bus contention would occur because the
8088
is
still driving the address on this bus. This
could cause
an
incorrect address
to
be
latched into the
8282
address latch.