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TEST
TEST
TEST
Encoding:
Memory or Register
Operand with Register Operand:
1100001
0 w 1
mod
reg
rIm 1
LSRC = REG, RSRC = EA
Immediate Operand with Memory or Register Operand:
11111
011
w 1
mod
000
rIm 1
data data
if
w=1
LSRC = EA, RSRC =
data
Immediate Operand with Accumulator:
11
0 1 0 1 0 0 w 1
data
1
data
if
w=1
if
w = 0
then
LSRC = AL, RSRC =
data
else
LSRC = AX, RSRC =
data
TEST
Operands
Clocks*
Transfers
register, register
3
-
register, memory
9(13)
+
EA
1
accumulator, immediate
4
-
register, immediate
5
-
memory, immediate
11(15)+EA
1
Bytes
TEST
Coding Example
2
TEST
SI,
DI
2-4
TEST
SI,
END~COUNT
2-3
TEST
AL,
00100000B
3-4
TEST
BX,
OCC4H
3-6
TEST
RETURN_CODE,
01
H
*b(w): where b denotes
the
number
of
clock
cycles
for
byte operands and w
denotes the
number
of
clock
cycles
for
word
operands.
2-159