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iAPX 88/10
The minimum mode
8088
can
be used with either a
multiplexed
or
demultiplexed bus. The multiplexed bus
configuration is
compatible with the MCS·85™ multi·
plexed
bus peripherals
(8155,
8156,
8355,
8755A, and
8185),
This configuration
(See
Figure
5)
provides the user
with a minimum chip count system. This architecture
provides the
8088
processing power in a highly integrated
form.
The
demultiplexed mode requires one latch (for 64K ad·
dressability) or two latches (for a full megabyte
of
ad·
dressing). A third latch can
be
used for buffering if the
address bus
loading requires it. An 8286 or
8287
trans·
ceiver can also
be
used
if
data bus buffering is required.
(See
Figure
6'>
The 8088 provides
DEN
and
DT/R
to
con·
43
trol the transceiver, and ALE
to
latch the addresses.
This configuration
of
the minimum mode provides the
standard
demuliiplexed bus structure
with
heavy bus
buffering and
relaxed bus timing requirements.
The maximum mode
employs the 8288 bus controller.
(See
Figure
7.)
The 8288 decodes status lines
SO,
S1,
and
S2,
and provides the system with all bus
control'
signals. Moving the bus control
to
the 8288 provides
better source and sink current
capability
to
the control
lines,
and frees the
8088
pins for extended large system
features. Han;jware
lock, queue status, and
two
requestl
grant interfaces are provided by the
8088 in maximum
mode. These features
allow co· processors in local bus
and remote
bus.
configurations.
AFN-OOB26D