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iAPX 88/10
before,
during,
or
after
the
servicing
of
NMI.
Another high-going edge triggers another response
if
it
occurs after the start of the N
MI
procedure. The signal
must be free
of
logical spikes in general and be free of
bounces on the low-going edge to avoid triggering
ex-
traneous responses.
Maskable Interrupt (INTR)
The 8088 provides a single interrupt request input (INTR)
which can
be
masked internally
by
software
with
the
resetting
of
the interrupt enable
(IF)
flag bit. The in-
terrupt request signal is level triggered. It is internally
synchronized during each
clock
cycle
on
the high-going
edge
of
CLK.
To
be responded to, INTR must
be
present
(HIGH) during the
clock
period preceding the end
of
the
current instruction
or
the enq of a whole move
for
a
block type instruction. During interrupt response
se-
quence, further interrupts are disabled. The enable
bit
is
reset as part of the response to any interrupt
(INTR,
NMI,
software interrupt,
or
single step), although the
FLAGS register which is automatically pushed onto the
stack reflects the state
of
the processor prior
to
the in-
terrupt. Until the old FLAGS register is restored, the
enable bit
will be zero unless specifically set by
an
in-
struction.
During the response sequence
(See
Figure
9),
the proc-
essor executes two successive (back to back) interrupt
acknowledge cycles. The
8088
emits the LOCK signal
(maximum mode only) from
T2
of
the first bus cycle until
T2
of
the second. A local bus
"hold"
request will not be
honored until the end
of
the second bus cycle.
In
the
second bus cycle, a byte is fetched from the external
in-
terrupt system (e.g., 8259A
PIC)
which identifies the
source (type) of the interrupt. This byte is
multiplied
by
four and used
as
a pointer into the interrupt vector
lookup table.
An
INTR signal left HIGH will
be
continual-
ly
responded to within the limitations of the enable bit
and sample period. The interrupt return instruction
in-
cludes a flags pop which returns the status
of
the
original interrupt enable bit when it restores the flags.
HALT
When a software HALT instruction is executed, the
processor indicates that it is entering the HALT state
in
one of
two
ways, depending upon which mode is
strapped.
In
minimum mode, the processor issues ALE,
delayed
by
one
clock
cycle,
to
allow the system
to
latch
the
halt status. Halt status is available
on
I
aiM',
DT/R,
and SSO.
In
maximum mode, the processor issues
ap-
propriate HALT status on
S2,
S1,
and
SO,
and the
8288
bus controller issues one ALE. The 8088 will not leave
the HALT state when a
local bus hold is entered while
in
HALT. In this case, the processor reissues the HALT in-
dicator at the end
of
the local bus hold.
An
interrupt
re-
quest
or
RESET
will force the 8088 out
of
the HALT
state.
Read/Modify/Write (Semaphore) Operations
via
LOCK
The LOCK status information is provided by the proc-
essor when consecutive bus cycles are required during
the execution of
an
instruction. This allows the proc-
essor
to
perform read/modify/write
operations
on
memory (via the
"exchange register
with
memory"
instruction), without another system bus master receiv-
ing intervening memory cycles. This is useful in multi-
processor system configurations to accomplish
"test
and set
lock"
operations. The
IOCR
signal is activated
(LOW) in the
clock
cycle following decoding of the
LOCK prefix instruction. It is deactivated at the end of
the
last bus cycle of the instruction following the LOCK
prefix. While
LOCK
is active, a request on a
RQ/GT
pin will
be
recorded, and then honored at the end of the
LOCK.
T1
\
T2 T3
T4
T1
I
T,
ALE
~L---_------,n~_-
FLOAT
ADo-AD7
\L--
__
----JI
Figure
9_
Interrupt Acknowledge Sequence
48
AFN-0082BO