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Booting and Self Tests
Chapter 6 Theory of Operation 51
The Combined Interface Board and the Modem Interface Board both have processors that
test the interface board once the DMA control logic has been checked.
The CPU Board boots a test program from the ROM to the on-board Digital Signal
Processor (DSP) program RAM. The DSP then runs it. The program tests the DSP and its
associated components, and writes the results to the DSP RAM. The CPU reads the RAM
to find out the exit status of the tests. If the test fails, the LED stays on and the error code is
displayed.
The signal processing software is stored as two programs in Flash EEPROMs. This carries
out US/US or US/ECG functions. The CPU Board transfers the US/US or US/ECG
program from its Flash EEPROMs to the program RAM of the DSP.
All the time the monitor is on, the CPU Board checksums the signal processing software
and the Flash EEPROMs at 1-minute intervals. If the tests fail, the system is reset and
rebooted. And every 300ms, a watchdog ASIC is fed patterns by the CPU Board 68000. If
the ASIC does not receive a pattern, it resets the system.