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Section 15 Serial Communication Interface with FIFO
Page 738 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
15.3.9 FIFO Control Register (SCFCR)
SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
-----
RSTRG[2:0] RTRG[1:0] TTRG[1:0] MCE TFRST RFRST LOOP
Bit Bit Name
Initial
Value R/W Description
15 to 11 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
10 to 8 RSTRG[2:0] 000 R/W RTS Output Active Trigger
When the quantity of receive data in receive FIFO data
register (SCFRDR) becomes more than the number
shown below, RTS signal is set to high.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14