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Section 13 Watchdog Timer
R01UH0134EJ0400 Rev. 4.00 Page 667 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
13.3.3 Watchdog Reset Control/Status Register (WRCSR)
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal
generated by watchdog timer counter (WTCNT) overflow.
Note: The method for writing to WRCSR differs from that for other registers to prevent
erroneous writes. See section 13.3.4, Notes on Register Access, for details.
76543210
00011111
R/(W) R/W R/W R R R R R
Bit:
Initial value:
R/W:
WOVF RSTE RSTS - - - - -
Bit Bit Name
Initial
Value R/W Description
7 WOVF 0 R/(W) Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
When 0 is written to WOVF after reading WOVF
6 RSTE 0 R/W Reset Enable
Selects whether to generate a signal to reset the LSI
internally if WTCNT overflows in watchdog timer
mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*
1: Reset when WTCNT overflows
Note: * LSI not reset internally, but WTCNT and
WTCSR reset within this module.
5 RSTS 0 R/W Reset Select
Selects the type of reset when the WTCNT overflows
in watchdog timer mode. In interval timer mode, this
setting is ignored.
0: Power-on reset
1: Manual reset
4 to 0
All 1 R Reserved
These bits are always read as 1. The write value
should always be 1.