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R01UH0134EJ0400 Rev. 4.00 Page 2091 of 2108
Sep 24, 2014
Item Page Revision (See Manual for Details)
37.4.3 Bus Timing
Figure 37.21 Synchronous
DRAM Single Write Bus
Cycle (Auto Precharge,
TRWL = 1 Cycle)
1996 Figure amended
D15 to D0
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
WDH2
t
WDD2
Figure 37.22 Synchronous
DRAM Single Write Bus
Cycle (Auto Precharge,
WTRCD = 2 Cycles, TRWL =
1 Cycle)
1997 Figure amended
D15 to D0
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
WDH2
t
WDD2
Figure 37.23 Synchronous
DRAM Burst Write Bus Cycle
(Four Write Cycles) (Auto
Precharge, WTRCD = 0
Cycle, TRWL = 1 Cycle)
1998 Figure amended
D15 to D0
t
RASD1
t
RASD1
RAS
t
CASD1
t
CASD1
CAS
t
DQMD1
t
DQMD1
DQMxx
t
WDH2
t
WDD2
t
WDH2
t
WDD2