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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 399 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
9, 8 PR[1:0] 00 R/W Priority Mode
These bits select the priority level between channels
when there are transfer requests for multiple channels
simultaneously.
00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 >
CH5 > CH6 > CH7 > CH8 > CH9 > CH10 > CH11
> CH12 > CH13 > CH14 > CH15
01: Fixed mode 2: CH0 > CH8 > CH1 > CH9 > CH2 >
CH10 > CH3 > CH11 > CH4 > CH12 > CH5 >
CH13 > CH6 > CH14 > CH7 > CH15
10: Setting prohibited
11: Setting prohibited
7 to 3 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
2 AE 0 R/(W)*
1
Address Error Flag
Indicates whether an address error has occurred by
this module. When this bit is set, even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1, DMA
transfer is not enabled. This bit can only be cleared by
writing 0 after reading 1.*
2
0: No address error occurred by this module
1: Address error occurred by this module
[Clearing condition]
Writing 0 after reading AE = 1*
2