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Section 26 USB 2.0 Host/Function Module
Page 1480 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Figure 26.2 shows a diagram relating to interrupts of this module.
USB bus reset detected
Set_Address detected
Set_Configuration
detected
Suspended state detected
BEMP interrupt enable register
Control write data stage
Control read data stage
Completion of control
transfer
Control transfer setup
reception
Control transfer error
VBSE
INTENB0 INTSTS0
RSME
SOFE
DVSE
CTRE
BEMPE
NRDYE
BRDYE
VBINT
RESM
SOFR
DVST
BCHGE
INTENB1 INTSTS1
DTCHE
SIGNE
SACKE
BCHG
DTCH
ATTCHE
EOFERRE
AT TC H
EOFERR
SIGN
SACK
CTRT
BEMP
NRDY
BRDY
:
:
b9
...
b1
b0
b9
b1
b0
BEMP interrupt
status register
NRDY interrupt enable register
:
:
b9
...
b1
b0
b9
b1
b0
NRDY interrupt
status register
BRDY interrupt enable register
:
:
b9
...
b1
b0
b9
b1
b0
BRDY interrupt
status register
Generation
circuit
Interrupt
request
.
.
.
.
.
.
.
.
.
Figure 26.2 Items Relating to Interrupts