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Section 32 General Purpose I/O Ports
R01UH0134EJ0400 Rev. 4.00 Page 1681 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Setting Register
Setting Mode Bit (PBnMD[1:0])
00 01 10
Function 1 Function 2 Function 3
PDCR0 PD3 D3 PWM1D
PD2 D2 PWM1C
PD1 D1 PWM1B
PD0 D0 PWM1A
Note: The function 2 of bus state controller and /or the function of NAND flush memory controller
change automatically. (See section 9, Bus State Controller.).
Table 32.6 Multiplexed Pins (Port E)
Setting Register
Setting Mode Bit (PEnMD[2:0])
000 001 010 011 100 101
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6
PECR1 PE5 SDA2 DV_HSYNC
PE4 SCL2 DV_VSYNC
PECR0 PE3 SDA1 IRQ3
PE2 SCL1 IRQ2
PE1 SDA0 IOIS16 IRQ1 TCLKA ADTRG
PE0 SCL0 AUDIO_CLK IRQ0