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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1611 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.29 SG Mode Register (SGMODE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
RRRRRRRRRRRRRRRR/W
0000000000000000
RRRRRRRRRRRRRRRR/W
------
-
---------
EX_
SYNC_
MODE
----- ---------
RGB565
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 17 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
16 EX_SYNC_
MODE
0 R/W Selects the sync signal mode.
0: Free-running mode
1: Synchronized with the Vsync of the video input
15 to 1 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 RGB565 0 R/W Specifies the method for conversion from RGB888
to RGB565.
0: Calculated as described in section 27.6.1 (4),
Conversion from RGB888 to RGB565.
1: Lower bits are truncated.