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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1031 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
TXCR0
1514131211109876543210
0000000000000000
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R
TXCR0[15:1]
Bit:
Initial value:
R/W:
-
Note: * Only writing a '1' to a Mailbox that is requested for transmission and is configured as
transmit.
Bit 15 to 1 — Requests the corresponding Mailbox, that is in the queue for transmission, to cancel
its transmission. The bit 15 to 1 corresponds to Mailbox-15 to 1 (and TXPR0[15:1]) respectively.
Bit[15:1]: TXCR0 Description
0 Transmit message cancellation idle state in corresponding mailbox (Initial
value)
[Clearing Condition]
Completion of transmit message cancellation (automatically cleared)
1 Transmission cancellation request made for corresponding mailbox
Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has
no effect and always read back as a ‘0’.
(3) Transmit Acknowledge Register (TXACK1, TXACK0)
The TXACK1 and TXACK0 are 16-bit read/conditionally-write registers. These registers are used
to signal to the CPU that a mailbox transmission has been successfully made. When a transmission
has succeeded this module sets the corresponding bit in the TXACK register. The CPU may clear
a TXACK bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect.
TXACK1
1514131211109876543210Bit:
Initial value:
R/W:
0000000000000000
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
TXACK1[15:0]
Note: * Only when writing a '1' to clear.