Filter
Top Products
Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1377 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000000000000000
R/W*
2
R/W*
1
RRRRRRRRRRRRRR
BVAL BCLR FRDY — DTLN[11:0]
Bit Bit Name
Initial
Value R/W Description
15 BVAL 0 R/W*
2
Buffer Memory Valid Flag
This bit should be set to 1 when data has been
completely written to the FIFO buffer on the CPU
side for the pipe selected using the CURPIPE bits
(selected pipe).
0: Invalid
1: Writing ended
When the selected pipe is in the transmitting
direction, set this bit to 1 in the following cases.
Then, this module switches the FIFO buffer from the
CPU side to the SIE side, enabling transmission.
To transmit a short packet, set this bit to 1 after
data has been written.
To transmit a zero-length packet, set this bit to 1
before data is written to the FIFO buffer.
Set this bit to 1 after the number of data bytes
has been written for the pipe in continuous
transfer mode, where the number is a natural
integer multiple of the maximum packet size and
less than the buffer size.
When the data of the maximum packet size has been
written for the pipe in non-continuous transfer mode,
this module sets this bit to 1 and switches the FIFO
buffer from the CPU side to the SIE side, enabling
transmission.
When the selected pipe is in the transmitting
direction, if 1 is written to BVAL and BCLR bits
simultaneously, this module clears the data that has
been written before it, enabling transmission of a
zero-length packet.
Writing 1 to this bit should be done while FRDY
indicates 1 (set by this module).
When the selected pipe is in the receiving direction,
do not set this bit to 1.