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Section 26 USB 2.0 Host/Function Module
Page 1466 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
7 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Notes: 1. Only 0 can be read and 1 can be written.
2. Modify each bit in this register while CSSTS is 0 and PID is NAK. Before modifying
each bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check
that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by
this module, checking PBUSY is not necessary.
26.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5)
PIPEnTRN is a transaction counter corresponding to PIPE1 to PIPE5.
This register is initialized by a power-on reset, but retains the set value by a USB bus reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TRNCNT[15:0]
Bit Bit Name
Initial
Value
R/W Description
15 to 0 TRNCNT[15:0] All 0 R/W Transaction Counter
When written to:
Specifies the number of transactions to be
transferred through DMA.
When read from:
Indicates the specified number of transactions if
TRENB is 0.
Indicates the number of currently counted
transaction if TRENB is 1.