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Page 2076 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Item Page Revision (See Manual for Details)
17.7.7 Note on Issuance of
Stop Conditions in Master
Transmit Mode while ACKE
= 1
891 Section added
18.1 Features
Figure 18.2 Block Diagram
of Serial Sound Interface
895 Figure amended
Peripheral bus
Interrupt/DMA
request
Control
circuit
Registers
SSICR
SSISR
SSIFCR
SSIFSR
SSITDR SSIRDR
SSIFTDR
(8-step FIFO)
SSIFRDR
(8-step FIFO)
18.3.5 FIFO Control
Register (SSIFCR)
911 Description amended
The SSIFCR register specifies the data trigger counts of
the transmit and receive FIFO data registers, and enables
or disables data resets and interrupt requests. SSIFCR can
always be read or written by the CPU.
911 to
913
Table amended
Bit Bit Name
Initial
Value
R/W Description
7, 6 TTRG[1:0] 00 R/W Transmit Data Trigger Count
These bits specify the transmit data count
(specified transmit trigger count) at which the TDE flag
in the FIFO status register (SSIFSR) is set during
transmission.
The TDE flag is set to 1 when the transmit
data count in the transmit FIFO data register (SSIFTDR)
is equal to or less than the specified trigger count shown
5, 4 RTRG[1:0] 00 R/W Receive Data Trigger Count
These bits specify the received data count
(specified receive trigger count) at which the RDF flag in
the FIFO status register (SSIFSR) is set during reception.
The RDF flag is set to 1 when the received data
count in the receive FIFO data register (SSIFRDR) is
equal to or more than the specified trigger count shown
below.
3 TIE 0 R/W Transmit Interrupt Enable
Enables or disables generation of transmit data empty
interrupt (TXI) requests during transmission when serial
transmit data is transferred from the transmit FIFO data
register (SSIFTDR) to the transmit data register
(SSITDR), the data count of the transmit FIFO data
register is less than the specified transmit trigger count,
and the TDE flag in the FIFO status register (SSIFSR)
is set to 1.
2 RIE 0 R/W Receive Interrupt Enable
Enables or disables generation of receive data full
interrupt (RXI) requests when the RDF flag in the FIFO
status register (SSIFSR) is set to 1 durin
g reception.
bel
ow.