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R01UH0134EJ0400 Rev. 4.00 Page 2083 of 2108
Sep 24, 2014
Item Page Revision (See Manual for Details)
26.4.4 FIFO Buffer Memory
(1) FIFO Buffer Memory
Allocation
1509 Description amended
When continuous transfer mode has been selected using
the CNTMD bit in PIPE CFG, the BUFSIZE bits should be
set so that the buffer memory size should be an integral
multiple of the maximum packet size. When double buffer
mode has been selected using the DBLB bit in PIPE CFG,
two planes of the memory area specified using the
BUFSIZE bits in PIPEBUF can be assigned to a single
pipe.
(a) Buffer Status 1510 Description amended
Tables 26.18 and 26.19 show the buffer status. The buffer
memory status can be confirmed using the BSTS bit in
DCPCTR and the INBUFM bit in PIPEnCTR. The access
direction for the buffer memory can be specified using
either the DIR bit in PIPE CFG or the ISEL bit in
CFIFOSEL (when DCP is selected).
(e) Buffer Memory
Specifications (Single/Double
Setting)
1513 Description amended
Either a single or double buffer can be selected for PIPE1
to PIPE5, using the DBLB bit in PIPE CFG.
(f) Buffer Memory Operation
(Continuous Transfer
Setting)
1514 Description amended
Either the continuous transfer mode or the non-continuous
transfer mode can be selected, using the CNTMD bit in
DCPCFG and PIPE CFG. This selection is valid for PIPE1
to PIPE5 and DCP.
Table 26.22 Relationship
between Transfer Mode
Settings by CNTMD Bit and
Timings at which Reading
Data or Transmitting Data
from FIFO Buffer is Enabled
1516 Table amended
Continuous or Non-
Continuous Transfer
Mode Method of Determining if Reading or Transmitting Data is Enabled
Continuous transfer
(CNTMD = 1)
In the receiving direction (DIR = 0), reading data from the FIFO buffer is
enabled when:
• The number of the data bytes received in the FIFO buffer assigned to
the selected pipe becomes the same as the number of assigned data
bytes (DCP: fixed at 256 bytes, pipes 1 to 5 (BUFSIZE + 1) × 64).
• This module receives a short packet other than a zero-length packet.
• This module receives a zero-length packet when data is already
stored in the FIFO buffer assigned to the selected pipe.
or
• This module receives the number of packets equal to the transaction
counter value specified for the selected pipe. (PIPE1 to PIPE5 only)
In the transmitting direction (DIR = 1), transmitting data from the FIFO
buffer is enabled when:
...
• In a DMA transfer, the DMA transfer end sampling enable (TENDE) bit
is set t
o 1, a number of data bytes less than the size of a single FIFO
buffer plane assigned to the selected pipe (or 0 bytes) is written to the
FIFO buffer, and the DMA transfer end signal is received (PIPE1 to
PIPE5 only).