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Section 9 Bus State Controller
Page 296 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
CKIO
A25 to A0
RD/WR
D15 to D0
DACKn
CSn
T1 T2 T1 T2
RD
WEn
BS
WAIT
D15 to D0
Read
Write
*
Note:
*
The waveform for DACKn is when active low is specified.
Figure 9.5 Continuous Access to Normal Space (2)
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1
(Access Wait = 0, Cycle Wait = 0)