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Section 10 Direct Memory Access Controller
Page 412 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(3) On-Chip Peripheral Module Request
In this mode, the transfer is performed in response to the DMA transfer request signal from an on-
chip peripheral module.
Table 10.7 lists the DMA transfer request signals sent from on-chip peripheral modules to this
module.
If DMA transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0),
AE = 0, and NMIF = 0) in on-chip peripheral module request mode, DMA transfer is started by a
transfer request signal.
In on-chip peripheral module request mode, there are cases where transfer source or destination is
fixed. For details, see table 10.7.
Table 10.7 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR DMARS DMA Transfer
Request
Source
DMA Transfer Request Signal
Transfer
Source
Transfer
Destination
Bus
Mode
RS[3:0] MID RID
1001 Any Any Controller area
network
Channel 0
RM0 (reception end) MB0 Any Cycle
steal
1010 Any Any Controller area
network
Channel 1
RM0 (reception end) MB0 Any
1000 000000 11 USB 2.0
host/function
module
USB_DMA0
(receive FIFO in channel 0 full)
D0FIFO Any
USB_DMA0
(transmit FIFO in channel 0
empty)
Any D0FIFO
000001 11 USB_DMA1
(receive FIFO in channel 1 full)
D1FIFO Any
USB_DMA1
(transmit FIFO in channel 1
empty)
Any D1FIFO