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Section 19 Serial I/O with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 957 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
19.3.7 FIFO Control Register (SIFCTR)
SIFCTR indicates the area available for the transmit/receive FIFO transfer.
Bit:
Initial Value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0001000000000000
R/W R/W R/W R R R R R R/W R/W R/W R R R R R
TFWM2 TFWM1 TFWM0 TFUA4 TFUA3 TFUA2 TFUA1 TFUA0 RFWM2RFWM1RFWM0 RFUA4 RFUA3 RFUA2 RFUA1 RFUA0
Bit Bit Name
Initial
Value R/W Description
15
14
13
TFWM2
TFWM1
TFWM0
0
0
0
R/W
R/W
R/W
Transmit FIFO Watermark
000: Issue a transfer request when 16 stages of the
transmit FIFO are empty.
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 12 or more stages of
the transmit FIFO are empty.
101: Issue a transfer request when 8 or more stages of
the transmit FIFO are empty.
110: Issue a transfer request when 4 or more stages of
the transmit FIFO are empty.
111: Issue a transfer request when 1 or more stages of
transmit FIFO are empty.
A transfer request to the transmit FIFO is issued by
the TDREQE bit in SISTR.
The transmit FIFO is always used as 16 stages of the
FIFO regardless of these bit settings.
12
11
10
9
8
TFUA4
TFUA3
TFUA2
TFUA1
TFUA0
1
0
0
0
0
R
R
R
R
R
Transmit FIFO Usable Area
Indicate the number of stages of FIFO that can be
transferred as B'00000 (full) to B'10000 (empty).