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Section 37 Electrical Characteristics
Page 2024 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 37.13 (2) I
2
C Bus Interface 3 Timing Clock Synchronized Serial Format
Item Symbol Min. Max. Unit Figure
SCL input cycle time t
SCL
12t
pcyc
*
1
+ 600 ns Figure 37.52
(2)
SCL input high pulse width t
SCLH
3t
pcyc
*
1
+ 300 ns
SCL input low pulse width t
SCLL
5t
pcyc
*
1
+ 300 ns
SCL, SDA input rise time t
Sr
300 ns
SCL, SDA input fall time t
Sf
300 ns
SCL, SDA input spike pulse removal time*
2
t
SP
1, 2 t
pcyc
*
1
Figure 37.52
(3)
Data output delay time t
HD
0 900 ns
Data input setup time t
SDAS
1t
pcyc
*
1
+ 20 ns
Data input hold time t
SDAH
0 ns
SCL, SDA capacitive load Cb 0 400 pF Figures
37.52 (2)
and
37.52 (3)
SCL, SDA output fall time*
3
t
Sf
250 ns
Notes: 1. t
pcyc
indicates the peripheral clock (P) cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristic.
t
SCL
t
SCLH
t
SCLL
t
Sf
t
Sr
SCL
Figure 37.52 (2) Clock Input/Output Timing
t
SDAS
t
SDAH
t
HD
SCL
SDA
Figure 37.52 (3) Transmission and Reception Timing