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Section 15 Serial Communication Interface with FIFO
R01UH0134EJ0400 Rev. 4.00 Page 747 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
15.4 Operation
15.4.1 Overview
For serial communication, this module has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses. Note that on the SH7262 channels other than 0 to 2, and on the
SH7264 channels other than 0 to 3, cannot be set to clock synchronous mode.
This module has a 16-stage FIFO buffer for both transmission and receptions, reducing the
overhead of the CPU, and enabling continuous high-speed communication. Furthermore, channel
1 on the SH7262, and channels 1 and 3 on the SH7264, have RTS and CTS signals to be used as
modem control signals.
The transmission format is selected in the serial mode register (SCSMR), as shown in table 15.9.
The clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control
register (SCSCR), as shown in table 15.10.
(1) Asynchronous Mode
Data length is selectable: 7 or 8 bits
Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding
selections constitutes the communication format and character length.
In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full,
overrun errors, receive data ready, and breaks.
The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
An internal or external clock can be selected as the clock source.
When an internal clock is selected, this module operates using the clock of on-chip baud
rate generator.
When an external clock is selected, the external clock input must have a frequency 16 or 8
times the bit rate. (The on-chip baud rate generator is not used.)