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Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00 Page 1323 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
25.4.3 Register Setting Procedure
Figure 25.3 shows the register setting flow required for accessing the flash memory.
Start
End
Start the setting procedure after the
current transfer has been completed
Not required in sector access
Not required in reading.
Not required when FLDTFIFO is used.
When the external bus mastership is
not released during data transfer, store
the control program for this module and
transfer data in the on-chip RAM
in advance.
Start the transfer
Wait until the transfer is completed
Note: Registers FLCMNCR to FLHOLDCR in this flow can be set in any order.
Ye s
No
FLTRCR = All 0?
Ye s
No
TREND in FLTRCR = 1?
Ye s
No
Except FLTRCR,
register settings completed?
Set FLCMNCR
Set FLCMDCR
Set FLCMCDR
Set FLADR
Set FLDTCNTR
Set FLDATAR
Set FLINTDMACR
Set FLBSYTMR
Set FLHOLDCR
Set FLTRCR to H'01
Set FLTRCR to H'00
When the fifth address data is output
in command access, FLADR2 should
also be set
Figure 25.3 Register Setting Flow