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Section 11 Multi-Function Timer Pulse Unit 2
Page 574 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(c) Buffer Transfer Control Linked with Interrupt Skipping
In complementary PWM mode, whether to transfer data from a buffer register to a temporary
register and whether to link the transfer with interrupt skipping can be specified with the BTE1
and BTE0 bits in the timer buffer transfer set register (TBTER).
Figure 11.70 shows an example of operation when buffer transfer is suppressed (BTE1 = 0 and
BTE0 = 1). While this setting is valid, data is not transferred from the buffer register to the
temporary register.
Figure 11.71 shows an example of operation when buffer transfer is linked with interrupt skipping
(BTE1 = 1 and BET0 = 0). While this setting is valid, data is not transferred from the buffer
register to the temporary register outside the buffer transfer-enabled period. Depending on the
rewrite timing from the interrupt generation to the buffer register, there are two types of the
transfer timing such as from the buffer register to the temporary register and from the temporary
register to the general register.
Note that the buffer transfer-enabled period depends on the T3AEN and T4VEN bit settings in the
timer interrupt skipping set register (TITCR). Figure 11.72 shows the relationship between the
T3AEN and T4VEN bit settings in TITCR and buffer transfer-enabled period.
Note: This function must always be used in combination with interrupt skipping.
When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0), make sure that buffer transfer is not linked with
interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to
0). If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled,
buffer transfer is never performed.