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Section 9 Bus State Controller
Page 314 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(3) Burst Read
A burst read occurs in the following cases with this LSI.
Access size in reading is larger than data bus width.
16-byte transfer in cache miss.
16-byte transfer in the direct memory access controller
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 8 times to read 16-byte continuous data from the SDRAM that
is connected to a 16-bit data bus. This access is called the burst read with the burst number 8.
Table 9.12 shows the relationship between the access size and the number of bursts.
Table 9.12 Relationship between Access Size and Number of Bursts
Bus Width Access Size Number of Bursts
16 bits 8 bits 1
16 bits 1
32 bits 2
16 bytes 8