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Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00 Page 819 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(3) MSB First Transfer (8-Bit Data)
Figure 16.10 shows the operation of the transmit buffer (SPDR) and the shift register when this
module performs an 8-bit data length MSB-first data transfer.
The CPU or direct memory access controller writes T07 to T00 to the transmit buffer. If the shift
register is empty, this module copies the data in the transmit buffer to the shift register, and fully
populates the shift register. When serial transfer starts, this module outputs data from bit 7 of the
shift register, and shifts in the data from the LSB (bit 0) of the shift register. When the RSPCK
cycle required for the serial transfer of 8 bits has passed, received data R07 to R00 is stored in bits
7 to 0 of the shift register. After completion of the serial transfer, data that existed before the
transfer is retained in bits 31 to 8 in the shift register. In this state, this module copies the data
from the shift register to the receive buffer, and empties the shift register. If the receive buffer
does not have a space for the receive data length after receive data has been copied from the shift
register to the receive buffer, another serial transfer will not be started. In order to start another
serial transfer, data for the receive data length should be read from the receive buffer to secure the
necessary area in the receive buffer.
If another serial transfer is started before the CPU or direct memory access controller writes to the
transmit buffer, received data R07 to R00 is shifted out from the shift register.