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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1509 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
26.4.4 FIFO Buffer Memory
(1) FIFO Buffer Memory Allocation
Figure 26.9 shows an example of a FIFO buffer memory map for this module. The FIFO buffer
memory is an area shared by the CPU and this module. In the FIFO buffer memory status, there
are times when the access right to the buffer memory is allocated to the user system (CPU side),
and times when it is allocated to this module (SIE side).
The buffer memory sets independent areas for each pipe. In the memory areas, 64 bytes comprise
one block, and the memory areas are set using the first block number of the number of blocks
(specified using the BUFNMB and BUFSIZE bits in PIPEBUF).
Independent buffer memory areas should be set for each pipe. Each memory area can be set using
the first block number and the number of blocks (specified using the BUFNMB and BUFSIZE bits
in PIPEBUF), where one block comprises 64 bytes.
When continuous transfer mode has been selected using the CNTMD bit in PIPECFG, the
BUFSIZE bits should be set so that the buffer memory size should be an integral multiple of the
maximum packet size. When double buffer mode has been selected using the DBLB bit in
PIPECFG, two planes of the memory area specified using the BUFSIZE bits in PIPEBUF can be
assigned to a single pipe.
Moreover, three FIFO ports are used for access to the buffer memory (reading and writing data). A
pipe is assigned to the FIFO port by specifying the pipe number using the CURPIPE bit in
C/DnFIFOSEL.
The buffer statuses of the various pipes can be confirmed using the BSTS bit in DCPCTR and the
INBUFM bit in PIPEnCTR. Also, the access right of the FIFO port can be confirmed using the
FRDY bit in CFIFOCTR or DnFIFOCTR.