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Section 20 Controller Area Network
Page 1034 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit[15:1]:ABACK0 Description
0 [Clearing Condition] Writing '1' (Initial value)
1 Corresponding Mailbox has cancelled transmission of message (Data or
Remote Frame)
[Setting Condition]
Completion of transmission cancellation for corresponding mailbox
Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has
no effect and always read back as a '0'.
(5) Data Frame Receive Pending Register (RXPR1, RXPR0)
The RXPR1 and RXPR0 are 16-bit read/conditionally-write registers. The RXPR is a register that
contains the received Data Frames pending flags associated with the configured Receive
Mailboxes. When a CAN Data Frame is successfully stored in a receive mailbox the
corresponding bit is set in the RXPR. The bit may be cleared by writing a '1' to the corresponding
bit position. Writing a '0' has no effect. However, the bit may only be set if the mailbox is
configured by its MBC (Mailbox Configuration) to receive Data Frames. When a RXPR bit is set,
it also sets IRR1 (Data Frame Received Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask
Register) is not set, and the interrupt signal is generated if IMR1 is not set. Please note that these
bits are only set by receiving Data Frames and not by receiving Remote frames.
RXPR1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit:
Initial value:
R/W:
0000000000000000
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
RXPR1[15:0]
Note : * Only when writing a '1' to clear.
Bit 15 to 0 — Configurable receive mailbox locations corresponding to each mailbox position
from 31 to 16 respectively.
Bit[15:0]: RXPR1 Description
0 [Clearing Condition] Writing '1' (Initial value)
1 Corresponding Mailbox received a CAN Data Frame
[Setting Condition]
Completion of Data Frame receive on corresponding mailbox