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Section 26 USB 2.0 Host/Function Module
Page 1502 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Register
Name Bit Name
Setting
Contents Remarks
DCPCTR
PIPEnCTR
ACLRM Auto buffer clear PIPE1 to PIPE9: Can be set
SQCLR Sequence clear Clears the data toggle bit
SQSET Sequence set Sets the data toggle bit
SQMON Sequence
monitor
Monitors the data toggle bit
PBUSY Pipe busy status
PID Response PID See section 26.4.3 (6), Response PID
PIPEnTRE TRENB Transaction
counter enable
PIPE1 to PIPE5: Can be set
TRCLR Current
transaction
counter clear
PIPE1 to PIPE5: Can be set
PIPEnTRN TRNCNT Transaction
counter
PIPE1 to PIPE5: Can be set
(1) Pipe Control Register Switching Procedures
The following bits in the pipe control registers can be modified only when USB communication is
disabled (PID = NAK):
Registers that Should Not be Set in the USB Communication Enabled (PID = BUF) State
Bits in DCPMAXP
The SQCLR, SQSET, and PINGE bits in DCPCTR
Bits in PIPECFG, PIPEBUF, PIPEMAXP and PIPEPERI
The ATREPM, ACLRM, SQCLR and SQSET bits in PIPEnCTR
Bits in PIPEnTRE and PIPEnTRN
Bits in DEVADDn
Note: In addition to the above, observe the setting procedures described in the register
descriptions regarding the settings of the CSCLR bit and DEVADDn register.
In order to modify the above bits from the USB communication enabled (PID = BUF) state, follow
the procedure shown below:
1. Generate a bit modification request with the pipe control register.
2. Modify the PID corresponding to the pipe to NAK.