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Section 22 Renesas SPDIF Interface
R01UH0134EJ0400 Rev. 4.00 Page 1159 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
12 UBUI 0 R/W User Buffer Underrun Interrupt Enable
Enables the user buffer underrun interrupts.
0: User buffer underrun interrupt disabled
1: User buffer underrun interrupt enabled
11 CREI 0 R/W Clock Recovery Error Interrupt Enable
Enables the clock recovery error interrupts.
0: Clock recovery error interrupt disabled
1: Clock recovery error interrupt enabled
10 PAEI 0 R/W Parity Error Interrupt Enable
Enables the parity check error interrupts.
0: Parity check error interrupt disabled
1: Parity check error interrupt enabled
9 PREI 0 R/W Preamble Error Interrupt Enable
Enables the preamble check error interrupts.
0: Preamble error interrupt disabled
1: Preamble error interrupt enabled
8 CSEI 0 R/W Channel Status Error Interrupt Enable
Enables the channel status error interrupts.
0: Channel status error interrupt disabled
1: Channel status error interrupt enabled
7 ABOI 0 R/W Audio Buffer Overrun Interrupt Enable
Enables the receiver audio buffer overrun interrupts.
0: Audio buffer overrun interrupt disabled
1: Audio buffer overrun interrupt enabled
6 ABUI 0 R/W Audio Buffer Underrun Interrupt Enable
Enables the transmitter audio buffer underrun interrupts.
0: Audio buffer underrun interrupt disabled
1: Audio buffer underrun interrupt enabled
5 RUII 0 R/W Receiver User Information Interrupt Enable
Enables the receiver user information register full
interrupts.
0: Receiver user information interrupt disabled
1: Receiver user information interrupt enabled