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Section 12 Compare Match Timer
R01UH0134EJ0400 Rev. 4.00 Page 657 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
CMCNT
CMCOR
N
N
0
Peripheral clock
(Pφ)
Counter clock
Compare match
signal
Clock
N + 1
Figure 12.4 Timing of CMF Setting
12.4.3 Timing of Compare Match Flag Clearing
The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of
the direct memory access controller being activated, the CMF bit is automatically cleared to 0
when data is transferred by the direct memory access controller.