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Page 2100 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
IREADY interrupt ................................ 1255
IRQ interrupts ......................................... 174
ISEC interrupt ....................................... 1254
ISY interrupt ......................................... 1255
ITARG interrupt ................................... 1254
J
Jump table base register (TBR) ................ 51
L
List of pins of this LSI .............................. 29
Load-store architecture ............................. 56
Local acceptance filter mask (LAFM) .... 997
Logic operation instructions ..................... 82
Loopback mode ...................................... 847
Low-frequency mode .............................. 333
Low-power SDRAM .............................. 339
LRU ........................................................ 211
M
Mailbox .......................................... 984, 988
Mailbox configuration ............................ 996
Mailbox control ...................................... 984
Manual reset ........................................... 140
Master receive operation ........................ 871
Master transmit operation ....................... 869
Memory-mapped cache .......................... 224
Message control field .............................. 993
Message data fields ................................. 998
Message receive sequence .................... 1073
Message transmission request ..... 1058, 1068
Micro processor interface (MPI) ............ 984
Module enabled mode ............................ 929
Module standby function ...................... 1817
MOSI signal value determination
during SSL negate period ....................... 809
Motor control PWM timer .................... 1829
Motor control PWM timer timing ......... 2044
MPX-I/O interface .................................. 301
Multi mode ............................................ 1271
Multi-function timer pulse unit 2 ............ 431
Multi-function timer pulse unit 2
timing .................................................... 2016
Multi-master mode operation .................. 833
Multiply and accumulate register high
(MACH) .................................................... 52
Multiply and accumulate register low
(MACL) .................................................... 52
Multiply/multiply-and-accumulate
operations .................................................. 57
N
NAND flash memory controller ........... 1287
NAND flash memory controller
interrupt requests ................................... 1338
NAND type flash memory controller
timing .................................................... 2030
NMI interrupt .......................................... 173
Noise filter .............................................. 881
Non-compressed modes .......................... 919
Nonlinearity error ................................. 1281
Non-numbers (NaN) ................................. 99
Normal space interface ........................... 294
Note on using a PLL oscillation circuit .. 129
O
Offset error ............................................ 1281
On-chip peripheral module interrupts ..... 176
On-chip peripheral module request ......... 412
On-chip RAM ....................................... 1671
Operation in asynchronous mode ............ 750
Operation in clocked synchronous mode 761
Output load circuit ................................ 2045
Output pin initialization for
multi-function timer pulse unit 2 ............ 616