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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 371 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 10 Direct Memory Access Controller
Direct Memory Access Controller can be used in place of the CPU to perform high-speed transfers
between external devices that have DACK (transfer request acknowledge signal), external
memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules.
10.1 Features
Number of channels: 16 channels (channels 0 to 15) selectable
Two channels (channels 0 and 1*) can receive external requests.
4-Gbyte physical address space
Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes
(longword 4)
Maximum transfer count: 16,777,216 transfers (24 bits)
Address mode: Dual address mode and single address mode are supported.
Transfer requests
External request
On-chip peripheral module request
Auto request
The following modules can issue on-chip peripheral module requests.
Serial communication interface with FIFO: 16 sources
I
2
C bus interface 3: six sources
A/D converter: one source
Multi-function timer pulse unit 2: five sources
Compare match timer: two sources
USB 2.0 host/function module: two sources
NAND flash memory controller: two sources
Controller area network: two sources
Serial sound interface: five sources
Sampling rate converter: four sources
Renesas SPDIF interface: two sources
CD-ROM decoder: one source
SD host interface: two sources
Renesas serial peripheral interface: four sources
Clock synchronous serial I/O with FIFO: two sources
Motor control PWM timer: two sources