Renesas R5S72647 Doll User Manual


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Section 23 CD-ROM Decoder
R01UH0134EJ0400 Rev. 4.00 Page 1197 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
23.3 Register Descriptions
This module has the following registers.
Table 23.1 Register Configuration
Name Abbreviation R/W
Initial
Value Address
Access
Size
Enable control register CROMEN R/W H'00 H'FFFF9000 8
Sync code-based synchronization control
register
CROMSY0 R/W H'89 H'FFFF9001 8
Decoding mode control register CROMCTL0 R/W H'82 H'FFFF9002 8
EDC/ECC check control register CROMCTL1 R/W H'D1 H'FFFF9003 8
Automatic decoding stop control register CROMCTL3 R/W H'00 H'FFFF9005 8
Decoding option setting control register CROMCTL4 R/W H'00 H'FFFF9006 8
HEAD20 to HEAD22 representation
control register
CROMCTL5 R/W H'00 H'FFFF9007 8
Sync code status register CROMST0 R H'00 H'FFFF9008 8
Post-ECC header error status register CROMST1 R H'00 H'FFFF9009 8
Post-ECC subheader error status register CROMST3 R H'00 H'FFFF900B 8
Header/subheader validity check status
register
CROMST4 R H'00 H'FFFF900C 8
Mode determination and link sector
detection status register
CROMST5 R H'00 H'FFFF900D 8
ECC/EDC error status register CROMST6 R H'00 H'FFFF900E 8
Buffer status register CBUFST0 R H'00 H'FFFF9014 8
Decoding stoppage source status register CBUFST1 R H'00 H'FFFF9015 8
Buffer overflow status register CBUFST2 R H'00 H'FFFF9016 8
Pre-ECC correction header:
minutes data register
HEAD00 R H'00 H'FFFF9018 8
Pre-ECC correction header:
seconds data register
HEAD01 R H'00 H'FFFF9019 8
Pre-ECC correction header:
frames (1/75 second) data register
HEAD02 R H'00 H'FFFF901A 8
Pre-ECC correction header:
mode data register
HEAD03 R H'00 H'FFFF901B 8